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1 www.semtech.com SC1403 mobile multi-output pwm controller with virtual current sense tm power management preliminary revision 3, august 2002 description features applications typical application circuit the SC1403 is a multiple-output power supply controller designed to power battery operated systems. the SC1403 provides synchronous rectified buck converter control for two (3.3 v and 5 v) power supplies. an effi- ciency of 95% can be achieved for the two supplies. the SC1403 uses semtech?s proprietary virtual current sense tm technology along with external error amplifier compensation to achieve enhanced stability and dc ac- curacy over a wide range of output filter components while maintaining fixed frequency operation. the SC1403 also provides a linear regulator for system housekeep- ing. the 5 v linear regulator takes its input from the battery; for efficiency, the output is switched to the 5v output when available. control functions include: power up sequencing, soft start, power-good signaling, and frequency synchroniza- tion. line and load regulation is to +/-1% of the output voltage. the internal oscillator can be adjusted to 200 khz or 300 khz or synchronized to an external clock. the mosfet drivers provide >1a peak drive current for fast mosfet switching. the SC1403 includes a psave# input to select pulse skipping mode for high efficiency at light load, or fixed frequency mode for low noise operation. ? 3.3v and 5v dual synchronous outputs, resistor programmable to 2.5v ? fixed frequency or psave for maximum efficiency over wide load current range ? 5v / 50ma linear regulator ? virtual current sense tm for enhanced stability ? accurate low loss current limiting ? out of phase switching reduces input capacitance requirements ? external compensation supports wide range of output filter components ? programmable power-up sequence ? power good output ? output overvoltage & overcurrent protection with output undervoltage shutdown ? 4a typical shutdown current ? 6mw typical quiescent power ? notebook and subnotebook computers ? automotive electronics ? desktop dc-dc converters 4 5 l2 l1 comp3 bst3 dh3 phase3 dl3 csh3 csl3 fb3 on3 on5 psav# gnd rst# ref seq fb5 csl5 csh5 pgnd dl5 phase5 dh5 bst5 comp5 sync v+ shdn# vl
2 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary electrical characteristics absolute maximum ratings r e t e m a r a pl o b m y sm u m i x a ms t i n u d n g o t + v , e g a t l o v y l p p u sv n i 0 3 + o t 3 . 0 -v d n g o t , 5 t s b , 3 t s b , s e g a t l o v t s o o b 6 3 + o t 3 . 0 -v d n g o t d n g p 3 . 0 v ; 5 e s a h p o t 5 t s b ; 3 e s a h p o t 3 t s b d n g o t 3 h s c , 3 l s c ; d n g o t 5 h s c , 5 l s c c d 6 + o t 3 . 0 - s n 0 0 1 , t n e i s n a r t 7 + o t 0 . 2 - v , 3 b f , l v , # t e s e r , 5 n o , # e v a s p , q e s , c n y s , f e r d n g o t 5 p m o c , 3 p m o c , 5 b f 6 + o t v 3 . 0 -v d n g o t # n d h s , 3 n o ) v 3 . 0 + + v ( o t v 3 . 0 -v d n g o t t r o h s f e r , l v s u o u n i t n o c t n e r r u c f e r 5 +a m t n e r r u c l v 0 5 +a m s d n o c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e lt d a e l 0 0 3 +c e g n a r e r u t a r e p m e t e g a r o t st g t s 0 0 2 + o t 5 6 -c e g n a r e r u t a r e p m e t n o i t c n u jt j 0 5 1 +c unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit r e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u s r e l l o r t n o c s p m s n i a m e g n a r e g a t l o v t u p n i 0 . 60 . 0 3v n i e g a t l o v t u p t u o v 3 . 3 e d o m e l b a t s u j d a , 3 b f o t d e i t 3 l s c , v 0 3 o t 0 . 6 = + v t i m i l t n e r r u c o t a 0 = d a o l v 3 5 4 . 25 . 25 5 . 2v n i e g a t l o v t u p t u o v 3 . 3 e d o m d e x i f , v 0 = 3 b f , v 0 3 o t 0 . 6 = + v t i m i l t n e r r u c o t a 0 = d a o l v 3 3 2 . 33 . 37 3 . 3v n i e g a t l o v t u p t u o v 5 e d o m e l b a t s u j d a , 5 b f o t d e i t 5 l s c , v 0 3 o t 0 . 6 = + v t i m i l t n e r r u c o t a 0 = d a o l v 5 5 4 . 25 . 25 5 . 2v n i e g a t l o v t u p t u o v 5 e d o m d e x i f , v 0 = 5 b f , v 0 3 o t 0 . 6 = + v t i m i l t n e r r u c o t a 0 = d a o l v 5 9 . 40 . 51 . 5v e g n a r t s u j d a e g a t l o v t u p t u os p m s r e h t i ef e r5 . 5v d l o h s e r h t e d o m e l b a t s u j d a e g a t l o v 5 . 08 . 01 . 1v n o i t a l u g e r d a o l t i m i l t n e r r u c o t a 0 , s p m s r e h t i e4 . 0 -% n o i t a l u g e r e n i l v = # e v a s p ; 0 3 < + v < v 0 . 6 , s p m s r e h t i e l 5 0 . 0v / % exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied.
3 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary electrical characteristics (cont.) r e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u i m i l - t n e r r u ctd l o h s e r h t3 l s c - 3 h s c , 5 l s c - 5 h s c0 40 50 7v m e v i t a g e nt i m i l c od l o h s e r h t 0 5 -v m d l o h s e r h t g n i s s o r c o r e z , v 0 = # e v a s p ; l s c - 3 h s c , 5 l s c - 5 h s c d e t s e t t o n 5v m e m i t p m a r t r a t s - t f o s o t t c e p s e r h t i w t i m i l t n e r r u c l l u f % 5 9 o t e l b a n e m o r f f c s o 2 1 5s k l c y c n e u q e r f r o t a l l i c s ol v = c n y s v 0 = c n y s 0 2 2 0 7 1 0 0 3 0 0 2 0 8 3 0 3 2 z h k r o t c a f y t u d m u m i x a ml v = c n y s v 0 = c n y s 2 9 4 9 4 9 6 9 % e s l u p h g i h t u p n i c n y sd e t s e t t o n0 0 3s n h t d i w e s l u p w o l t u p n i c n y sd e t s e t t o n0 0 3 e m i t l l a f / e s i r c n y sd e t s e t t o n0 0 2 e g n a r y c n e u q e r f t u p n i c n y s 0 4 20 5 3z h k e g a k a e l t u p n i e s n e s - t n e r r u c t n e r r u c v 5 . 5 = 5 h s c = 3 h s c30 1a p m a r o r r e n i a g p o o l d e s o l c 8 1v / v h t d i w d n a b p o o l d e s o l c 8z h m e c n a t s i s e r t u o5 p m o c , 3 p m o c5 15 25 3k ? e g a t l o v t e s f f of e r - b f l a n r e t n i2 v m e c n e r e f e r d n a r o t a l u g e r l a n r e t n i e g a t l o v t u p t u o l v; v 0 3 < + v < v 6 ; + v = # n d h s i < a m 0 d a o l v 0 = 5 n o = 3 n o ; a m 0 5 < 6 . 42 . 5v t u o k c o l e g a t l o v r e d n u l v d l o h s e r h t t l u a f v 7 . 0 = s i s e r e t s y h , e g d e g n i l l a f5 . 37 . 30 . 4 t u o k c o l r e v o h c t i w s l vp u t r a t s t a r e v o h c t i w s5 . 4 e g a t l o v t u p t u o f e rd a o l l a n r e t x e o n5 4 . 25 . 25 5 . 2 n o i t a l u g e r d a o l f e ri < a 0 d a o l a 0 5 <5 . 2 1v m i < a m 0 d a o l a m 5 <0 5 unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit
4 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary r e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u t n e r r u c k n i s f e r 0 1a e g a t l o v t u o k c o l t l u a f f e re g d e g n i l l a f8 . 12 . 2v t n e r r u c y l p p u s g n i t a r e p o + v , n o s p m s h t o b , 5 t u o v o t r e v o d e h c t i w s l v a 0 = 5 d a o l i , a 0 = 3 d a o l i 0 10 5a t n e r r u c y l p p u s y b d n a t s + v, f f o s p m s , v 0 3 o t v 6 = + v # n d h s o t n i t n e r r u c s e d u l c n i 0 8 1 t n e r r u c y l p p u s n w o d t u h s + vv 0 = # n d h s , v 0 3 o t v 6 = + v40 1 n o i t p m u s n o c r e w o p t n e c s e i u q , v 0 = 5 b f = 3 b f , d e l b a n e s p m s s p m s n o d a o l o n 0 . 6w m n o i t c e t e d t l u a f d l o h s e r h t p i r t e g a t l o v r e v o e g a t l o v t u p t u o d e d a o l n u o t t c e p s e r h t i w70 15 1% t l u a f - e g a t l o v r e v o y a l e d n o i t a g a p o r p v p i r t e g a t l o v r e v o e v o b a % 2 n e v i r d t u p t u o h t 5 . 1s d l o h s e r h t e g a t l o v r e d n u t u p t u o e g a t l o v t u p t u o d e d a o l n u o t t c e p s e r h t i w5 65 75 8% t u o k c o l e g a t l o v r e d n u t u p t u o e m i t f o t t c e p s e r h t i w , d e l b a n e s p m s h c a e m o r f c s o 0 0 0 54 4 1 60 0 0 7s k l c d l o h s e r h t n w o d t u h s l a m r e h tc 0 1 + = s i s e r e t s y h l a c i p y t0 5 1c # t e s e r d l o h s e r h t p i r t # t e s e r , e g a t l o v t u p t u o d e d a o l n u o t t c e p s e r h t i w % 1 = s i s e r e t s y h l a c i p y t ; e g d e g n i l l a f 3 1 -0 1 -7 -% y a l e d n o i t a g a p o r p # t e s e r w o l e b % 2 n e v i r d t u p t u o , e g d e g n i l l a f d l o h s e r h t p i r t # t e s e r 5 . 1s e m i t y a l e d # t e s e rf o t t c e p s e r h t i w c s o 0 0 0 , 7 20 0 0 , 2 30 0 0 , 7 3 s k l c s t u p t u o d n a s t u p n i t n e r r u c e g a k a e l t u p n i k c a b d e e fv 6 . 2 = 5 b f , 3 b f+1a e g a t l o v w o l t u p n i c i g o l c n y s , # n d h s , 5 n o , # e v a s p , 3 n o ) l v r o v 0 = q e s ( 6 . 0v e g a t l o v h g i h t u p n i c i g o l c n y s , # n d h s , 5 n o , # e v a s p , 3 n o ) l v r o v 0 = q e s ( 4 . 2v electrical characteristics (cont.) unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit
5 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary electrical characteristics (cont.) r e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u t n e r r u c e g a k a e l t u p n i c n y s , # n d h s , 5 n o , # e v a s p , 3 n o ) l v r o v 0 = q e s ( +1 a e g a t l o v w o l t u p t u o c i g o la m 4 = k n i s i , # t e s e r4 . 0v t n e r r u c h g i h t u p t u o c i g o lv 5 . 3 = # t e s e r1a m e c n a t s i s e r n w o d - l l u p 5 n of e r = q e s , v 0 = 3 n o , 5 n o0 0 1 ? e c r u o s / k n i s r e v i r d e t a g t n e r r u c v 5 . 2 o t d e c r o f , 5 h d , 5 l d , 3 h d , 3 l d1a e c n a t s i s e r - n o r e v i r d e t a gw o l r o h g i h5 . 17 ? d l o h s e r h t p a l r e v o - n o n 5 l d r o , 3 l d , 5 e s a h p , 3 e s a h p0 . 1v y a l e d p a l r e v o - n o n l d f o e g d e g n i s i r o t h d f o e g d e g n i l l a f h d f o e g d e g n i s i r o t l d f o e g d e g n i l l a f , l d d n a h d n o d l o h s e r h t v 1 ( ) h d r o l d n o e c n a t i c a p a c o n 0 1 5 3 7 1 5 7 5 2 5 1 1 c e s n c e s n unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit note: (1) this device is esd sensitive. use of standard esd handling precautions required.
6 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary pin configuration ordering information e c i v e de g a k c a pt ( . p m e t a ) r t s t i 3 0 4 1 c s8 2 - p o s s tc 5 8 + - 0 4 - block diagram 1 2 3 4 5 6 7 8 on3 csh3 top view (28 pin tssop) 27 28 15 16 dh3 csl3 phase3 fb3 bst3 comp3 dl3 comp5 shdn# sync v+ on5 vl gnd 9 10 22 pgnd ref dl5 psave# 21 18 17 19 20 11 12 24 bst5 reset# phase5 fb5 23 25 26 13 14 dh5 csl5 seq csh5 note: (1) only available in tape and reel packaging. a reel contains 2500 devices.
7 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary pin descriptions # n i pe m a n n i pn o i t c n u f n i p 13 h s c. s p m s v 3 . 3 r o f t u p n i e s n e s t i m i l t n e r r u c . r o t s i s e r e s n e s t n e r r u c a f o e d i s r o t c u d n i e h t o t t c e n n o c 23 l s c. s p m s v 3 . 3 r o f t u p n i e s n e s e g a t l o v t u p t u o . r o t s i s e r e s n e s t n e r r u c a f o e d i s t u p t u o e h t o t t c e n n o c 33 b f . e d o m e l b a t s u j d a n i ) v 5 . 2 . x o r p p a ( f e r = 3 b f t a s e t a l u g e r ; s p m s v 3 . 3 e h t r o f t u p n i k c a b d e e f r o t s i s e r a o t 3 b f t c e n n o c . d n g o t d e i t n e h w g n i t t e s e g a t l o v t u p t u o d e x i f v 3 . 3 e h t s t c e l e s 3 b f . e d o m t u p t u o e l b a t s u j d a r o f r e d i v i d 43 p m o c. s p m s v 3 . 3 r o f r e i f i l p m a r o r r e e h t f o t u p t u o e h t 55 p m o c. s p m s v 0 . 5 r o f r e i f i l p m a r o r r e e h t f o t u p t u o e h t 6c n y s r o f d n g o t e i t ; n o i t a r e p o z h k 0 0 3 r o f l v o t e i t . t c e l e s y c n e u q e r f d n a n o i t a z i n o r h c n y s r o t a l l i c s o . z h k 0 5 3 d n a z h k 0 4 2 n e e w t e b c n y s o t y l l a n r e t x e n e v i r d . z h k 0 0 2 75 n o. t u p n i l o r t n o c f f o / n o v 5 8d n g. t n i o p e c n e r e f e r k c a b d e e f d n a d n u o r g g o l a n a e s i o n w o l 9f e r . m u m i n i m f 1 h t i w d n g o t s s a p y b . t u p t u o e g a t l o v e c n e r e f e r v 5 . 2 0 1# e v a s p . e s u l a m r o n r o f d n g o t t c e n n o c . h g i h n e h w e d o m e v a s p s e l b a s i d t a h t t u p n i l o r t n o c c i g o l 1 1# t e s e r k c o l c 0 0 0 , 2 3 d e x i f a r e t f a h g i h s e o g . l v o t d n g s g n i w s # t e s e r . t u p t u o t e s e r d e m i t w o l e v i t c a . p u r e w o p g n i w o l l o f y a l e d e l c y c 2 15 b f 5 b f . e d o m e l b a t s u j d a n i ) v 5 . 2 . x o r p p a ( f e r = 5 b f t a s e t a l u g e r ; s p m s v 5 r o f t u p n i k c a b d e e f r o f r e d i v i d r o t s i s e r a o t 5 b f t c e n n o c . d n g o t d e i t n e h w g n i t t e s e g a t l o v t u p t u o d e x i f v 5 e h t s t c e l e s . e d o m t u p t u o e l b a t s u j d a 3 15 l s c. s p m s v 5 r o f t u p n i e s n e s e g a t l o v t u p t u o . r o t s i s e r e s n e s t n e r r u c a f o e d i s t u p t u o e h t o t t c e n n o c 4 15 h s c. s p m s v 5 r o f t u p n i e s n e s t i m i l t n e r r u c . r o t s i s e r e s n e s t n e r r u c a f o e d i s r o t c u d n i e h t o t t c e n n o c 5 1q e s. # t e s e r r o f e c n e u q e s s p m s s t c e l e s t a h t t u p n i 6 15 h d. h c t i w s l e n n a h c - n e d i s h g i h , v 5 e h t r o f t u p t u o e v i r d e t a g 7 15 e s a h p. n o i t c e n n o c ) r o t c u d n i ( e d o n g n i h c t i w s 8 15 t s b. e v i r d e t a g e d i s h g i h r o f n o i t c e n n o c r o t i c a p a c t s o o b note: all logic level inputs and outputs are open collector ttl compatible.
8 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary pin descriptions (cont.) 2.5v ref v+ +3.3v vl vin vl bst3 dh3 lx3 dl3 csh3 csl3 comp3 ref time/on5 run/on3 seq reset comp5 csl5 csh5 pgnd dl5 lx5 dh5 bst5 vl sync v+ psave 5v reg en delay csl5 vl ls osc ls hs vl 50mv 7.5m v 2.5m v 3v ctl logic oc ps pol 50mv 7.5m v 2.5m v oc ps pol 5v ctl logic pw m modulator pw m modulator ov fault +10% -25% uv fault 3 vl 2 pow er-on sequence logic 0.5 2.0 ss timer bv delay +5v vin fb5 0.6 fb3 0.6v current ramp v+ csl3 csl5 # n i pe m a n n i pn o i t c n u f n i p 9 15 l d. t e f s o m r e i f i t c e r s u o n o r h c n y s e d i s w o l e h t r o f t u p t u o e v i r d e t a g 0 2d n g p. d n u o r g r e w o p 1 2l v. t u p t u o r o t a l u g e r r a e n i l l a n r e t n i v 5 2 2+ v. t u p n i e g a t l o v y r e t t a b 3 2# n d h s. w o l e v i t c a , t u p n i l o r t n o c n w o d t u h s 4 23 l d. t e f s o m r e i f i t c e r s u o n o r h c n y s e d i s w o l e h t r o f t u p t u o e v i r d e t a g 5 23 t s b. e v i r d e t a g e d i s h g i h r o f n o i t c e n n o c r o t i c a p a c t s o o b 6 23 e s a h p. n o i t c e n n o c ) r o t c u d n i ( e d o n g n i h c t i w s 7 23 h d. h c t i w s l e n n a h c - n e d i s h g i h , v 3 . 3 e h t r o f t u p t u o e v i r d e t a g 8 23 n o. t u p n i l o r t n o c f f o / n o note: all logic level inputs and outputs are open collector ttl compatible. block diagram
9 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary functional information detailed description the SC1403 is a versatile multiple-output power supply controller designed to power battery operated systems. out of phase switching design is adopted to improve signal quality and reduce input rms current, therefore reducing size of input filter inductor and capacitors. the SC1403 provides synchronous rectified buck control in fixed frequency forced-continuous mode and hysteretic psave mode for two switching power supplies over a wide load range. the two switchers have on-chip preset output voltage of 5.0v and 3.3v. an external resistor divider can be used to set the switcher outputs from 2.5v to 5.5v. the control and fault monitoring circuitry associated with each pwm controller includes digital softstart, turn-on sequencing, voltage error amplifier with built-in slope compensation, pulse width modulator, power save, over-current, over-voltage and under-voltage fault protection. one linear regulator and a precision reference voltage are also provided by the SC1403. the 5v/50ma linear regulator takes input from the battery to power the gate drivers, however to improve efficiency, the 5v switcher output is used instead when available. semtech?s proprietary virtual current sense tm provides greater advantages in the aspect of stability and signal to noise ratio than the conventional current sense method. pwm control there are two separate pwm control blocks for the 3v and 5v switchers. they are out-of-phase with each other. the interleaved topology offers greater advantage over in-phase solutions. it reduces steady state input filter requirements by reducing current drawn from the filter capacitors. to avoid both switchers switching at the same instance, there is a built-in delay between the on-time of the 3.3v switcher and 5v switcher, the amount of which depends on the input voltage (see out-of-phase switching). the pwm provides two modes of control over the entire load range. the SC1403 operates in forced continuous conduction mode as a fixed frequency peak current mode controller with falling edge modulation. current sense is done differently than that in the conventional peak current mode control. semtech?s proprietary virtual current sense tm emulates the necessary inductor current information for proper functioning of the ic. in order to accommodate a wide range of output filters, a comp pin is also available for compensating the error amplifier externally. a nominal gain of 18 is used in the error amplifier to further improve the system loop gain response and the output transient behavior. when the switcher is operating in continuous conduction mode, the high- side mosfet is turned on at the beginning of each switching cycle. it is turned off when the desired duty cycle is reached. active shoot- through protection delays the turn-on of the lower mosfet until the phase node drops below 2.5v. the low-side mosfet remains on until the beginning of the next switching cycle. again, active shoot-through protection ensures that the gate to the low-side mosfet has dropped low before the high-side mosfet is turned on. under light load conditions when the psave pin is low, the SC1403 operates as a hysteretic controller in the discontinuous conduction mode to reduce its switching frequency and switching bias current. the switching of the output mosfet does not depend on a given oscillator frequency, but on the hysteretic fb trip voltage set around the reference. when entering psave mode, if the minimum (valley) inductor current measured across the csh and csl pins is below the psave threshold for four switching cycles, the virtual current sensing circuitry is shutdown and pwm switches from forced continuous to hysteretic mode. if the minimum (valley) inductor current is above the threshold for four switching cycles, pwm control changes from hysteretic to forced continuous mode. the SC1403 provides built-in hysteresis to prevent chattering between the two modes of operation. gate drive / control the gate drivers on the SC1403 are designed to switch large mosfets up to 350khz. the high-side gate driver is required to drive the gates of high-side mosfet above the v+ input. the supply for the gate drivers is generated by charging a boostrap capacitor from the vl supply when the low-side driver is on. monitoring circuitry ensures that the bootstrap capacitor is charged when coming out of shutdown or fault conditions where the bootstrap capacitor may be depleted. in continuous conduction mode, the low-side driver output that controls the synchronous rectifier in the power stage is on when the high-side driver is off. under light load conditions when psave pin is low, the inductor ripple current will approach the point where it reverses polarity. this is detected by the low-side driver control and the synchronous rectifier is turned off before the current reverses, preventing energy drain from the output. the low-side driver operation is also affected by various fault conditions as described in the fault protection section. internal bias supply the vl linear regulator provides a 5v output that is used to power the gate drivers, 2.5v reference and internal control section of the SC1403. the regulator is capable of supplying up to 50ma (in- cluding mosfet gate charge current). the vl pin should be by- passed to gnd with 4.7uf to supply the peak current require- ments of the gate driver outputs. the regulator receives its input power from the v+ battery input. efficiency is improved by provid- ing a boot-strapping mode for the vl bias. when the 5v smps output voltage reaches 5v, internal circuitry detects this condition and turns on a pmos pass device between csl5 and vl. the internal vl regulator is then disabled and the vl bias is provided by the high efficiency switcher. the ref output is accurate to +/- 2% over temperature. it is capable of delivering 5ma max and should be bypassed with 1uf minimum capacitor. loading the ref pin will reduce the ref voltage slightly.
10 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary functional information current sense (csh, csl) the output current of the power supply is sensed as the voltage drop across an external resistor between csh and csl pins. over- current is detected when the current sense voltage exceeds +/- 50mv. a positive over-current will turn off the high-side driver; a negative over-current will turn off the low-side driver, each on a cycle by cycle basis. oscillator when the sync pin is set high the oscillator runs at 300khz; when sync is set low the frequency is 200khz. the oscillator can also be synchronized to the falling edge of a clock on the sync pin with a frequency between 240khz and 350khz. in general, 200khz operation is used for highest efficiency, and the 300khz for minimum output ripple and/or smaller filter components. fault protection in addition to cycle-by-cycle current limit, the SC1403 monitors over-temperature, and output over-voltage and under-voltage conditions. the over-temperature detect will shut the part down if the die temperature exceeds 150 c with 10 c of hysteresis. if either smps output is more than 10% above its nominal value, both smps are latched off and synchronous rectifiers are latched on. to prevent the output from ringing below ground in a fault condition, a 1a schottky diode should be placed across each output. two different levels of undervoltage are detected. if the output falls 10% below its nominal output, the reset output is pulled low.if the output falls 25% below its nominal output following a start-up delay, both smps are latched off. both of the latched fault modes persist until shdn or run/on3 is toggled or the v+ input is brought below 1v. output voltage selection if fb is connected to ground, internal resistors setup 3.3v and 5v output voltages. if external resistors are used, the internal feedback is disabled and the output is regulated based on 2.5v reference at the fb pin. (see comment in the application design section). power up controls and soft start the user has control of the SC1403 reset# by setting the seq, on3 and on5 pins as described in the following table. each smps contains its own counter and dac to gradually increase the current limit at startup to prevent surge currents. the current limit is increased from 0, 20%, 40%, 60%, 80%, to 100% linearly over the course of 512 switching cycles. a reset# output is also generated at startup. the reset# pin is held low for 32k switching cycles. another timer is used to enable the undervoltage protection. the undervoltage protection circuitry is enabled after 6144 switching cycles at which time the smps should be in regulation. when seq is set to ref, the reset# pin only monitors the 3.3v smps in regulation and the 5v smps is ignored. applications information reference circuit design reference circuit design reference circuit design reference circuit design reference circuit design introduction introduction introduction introduction introduction the SC1403 is a versatile dual switching regulator adjustable from 2.5v to 5.5v with fixed 5v and 3.3v modes. in addition, there is an on-chip 5v linear regulator capable of supplying 50ma shutdown and operating modes shutdown and operating modes shutdown and operating modes shutdown and operating modes shutdown and operating modes holding the shdn pin low disables the SC1403, reducing the v+ input current to less than 10ua. when shdn goes high, the part enters a standby mode where the vl regulator and vref are enabled. turning on either smps will put the SC1403 in run mode. n d h s3 n o5 n oe d o mn o i t p i r c s e d w o lxx - t u h s n w o d s a i b m u m i n i m t n e r r u c h g i hw o lw o ly b d n a t sl v d n a f e r v r o t a l u g e r e l b a n e h g i hh g i hh g i hn u r e d o m s p m s h t o b g n i n n u r output current. the SC1403 is designed for notebook applications but has applications where high efficiency, small package and low cost are required. g n i d a o l e c n a t s i s e r ) m h o ( 1 1 5k 7 6 . 2k 9 . 9 4k 5 5 2g e m 1 n o i t a i v e d = f e r v m o r f v 0 2 9 4 . 2 v m 3 . 8v m 1 . 3v m 5 . 0v m 3 . 0v m 0
11 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary SC1403 startup sequence chart design guidelines the schematic for the reference circuit is shown on page 24. the reference circuit is configured as follows: switching regulator 1 vout1 = 3.3v @ 6a switching regulator 2 vout2 = 5.0v @ 6a linear regulator vout3 = 5.0v @ 50ma designing the output filter before calculating the output filter inductance and output capacitance, an acceptable amount of output ripple current is to be determined. the maximum allowable ripple current depends on the transient requirement of the power supply. under normal situation, the ripple current is usually set at 10 to 20% of the maximum load. however, in order to speed up the output transient response, ripple current can be much higher. in this design, we are going to set the ripple current to be 40% of maximum load. so once the ripple voltage specification is determined, the capacitor esr is chosen. the output ripple voltage is usually specified at +/ - 1% of the output voltage. functional information (cont.) for the reference circuit 3.3v switcher, we selected a maximum ripple voltage of 33mv. choosing one 180uf, 4v panasonic sp polymer aluminum electrolytic cap, of which esr is 15 ? m , sets the maximum ripple current as follows: checking to see if the maximum rms current can be met by the sp cap. irms=0.635 a << irms_rated=3.0a the output inductance can now be found by: q e s3 n o5 n ot e s e rn o i t p i r c s e d f e rw o lw o l. s p m s v 3 . 3 s w o l l o f . f f o s s p m s h t o b . e d o m l o r t n o c t r a t s t n a d n e p e d n i f e rw o lh g i h. w o l. f f o s p m s v 3 . 3 , n o s p m s v 5 f e rh g i hw o l. s p m s v 3 . 3 s w o l l o f. f f o s p m s v 5 , n o s p m s v 3 . 3 f e rh g i hh g i h. s p m s v 3 . 3 s w o l l o f. n o s s p m s h t o b d n gw o lx . w o l. f f o s s p m s h t o b d n gh g i hw o l / h g i he r a s t u p t u o h t o b r e t f a h g i h . n o i t a l u g e r n i , h g i h = 5 n o f i . h g i h s e o g 3 n o n e h w s t r a t s v 5 . f f o s i v 3 , w o l = 3 n o f i . n o s i v 3 l vw o lx . w o l. f f o s s p m s h t o b l vh g i hw o l / h g i he r a s t u p t u o h t o b r e t f a h g i h . n o i t a l u g e r n i , h g i h = 5 n o f i . h g i h s e o g 3 n o n e h w s t r a t s v 3 . f f o s i v 5 , w o l = 3 n o f i . n o s i v 5 applications information 3 i i i i i 2 2 2 1 2 1 rms + ? + = o s nom o nom _ in o i t d ) v v ( l ? ? ? ? = esr v i max _ o o ? = ? a 2 . 2 015 . 0 v 033 . 0 i o = ? = ? 2 i i o 1 ? ? = 2 i i o 2 ? + =
12 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary applications information where vin_nom=15v, vo=3.3v, d=vo/vin_nom, fs=300khz, ts=3.33us and io=2.2 a. lo is subsequently calculated to be 3.9uh. for the interest of this design, lo is chosen to be 4.7uh. choosing current sense resistor since the SC1403 implements virtual current sense tm , the exter- nal current sense resistor is not required for the control loop. how- ever, it is required for cycle-by-cycle current limit. cycle-by-cycle current limit is enabled when the voltage across the current sense resistor exceeds 50mv nominal. depending on the system re- quirement, this current limit can vary, it is usually 10 to 30% higher than the maximum load. taking into consideration of the +/-20% variation on the 50mv, the value of the current sense resistor can be calculated using the following equation: for a dc oc trip point between 6.3a to 9.8a, rsense is chosen to be 5.5m ? . considering the maximum power dissipation, two vishay wsl2010 11m ? 1% resistors are used. choosing the main switching mosfet before choosing the main switch mosfet, we need to know two critical parameters: voltage and current rating. in order to mini- mize the conduction loss, we recommend using the lowest rds(on) for the same voltage and current rating. the maximum drain to source voltage of the switch mosfet is mainly decided by the topology of the switcher. since this is a buck topology, applying a derating of 70%, a 30v mosfet is used in the design. the peak current of the mosfet is determined by the following calculations are done to verify that the power dissi- pation of the main switch mosfet is well within 1.86w, which is the maximum allowable power dissipation for the package. where rds(on) = 0.01 ? @tj=25 c and vgs = 4.5v. in order to find rds(on)@ tj=100 c , use 1.40*rds(on)@25 c . therefore, rds(on) @ tj = 100 c is equal to 0.014 ? . where = 7.1a, = 4.9a and the worst case conduction loss is calculated to be 112mw. and the switching loss of the mosfet is given by, where crss is the reverse transfer capacitance of the mosfet; it is equal to 200pf for sts12nf30l, ig is the gate driver current; it is equal to 1a for SC1403. and vin_nom = 15v, fs = 300khz. the switching loss is calculated to 81mw. and the gate loss is given by, where cg=11nf, v=5v and fs=300khz. the gate loss is calcu- lated to be 41mw. so the total power dissipation is calculated to be 234mw and is well within the maximum power dissipation allowance of the mosfet. no special heating sinking is required when laying out the mosfet. according to the calculated voltage and current rating, si4886dy, irf7413, fds9412 or sts12nf30l meets the requirement. the specs for these mosfets are listed in the table below. for the purpose of this exercise, sts12nf30l is chosen. next step is to determine its power handling capability. based on 85 c ambient temperature, 150 c junction temperature and 50 c /w ther- mal resistance, its power handling is calculated as follows: ? t j = 150c; t a = 85c; = 50c/w n / p r o d n e v) v ( s d v) a ( d i) n 0 ( s d r v 5 . 4 @ ) m h o ( e g a k c a p y d 6 8 8 4 i s0 33 15 3 1 0 . 08 - o s 3 1 4 7 f r i0 33 11 1 0 . 08 - o s 2 1 4 9 s d f0 39 . 76 3 0 . 08 - o s l 0 3 f n 2 1 s t s0 32 15 8 0 0 . 08 - o s ja s 2 g gate f v c 2 1 p ? ? ? = ) 3 i i i i ( i 2 2 2 1 2 1 rms + ? + = 2 i i i max _ o max 1 ? + = gate switching conduction diss _ total p p p p + + = nom 2 rms ) on ( ds conduction d i r p ? ? = g out s 2 in rss switching i i f v c p ? ? ? = nom _ in out nom v v d = v 21 v v max _ in max _ ds = = 2 i i i max _ o max 2 ? ? = 1.30w 50 85 150 t t p ja a j t = ? = ? = a 11 m 5 . 5 mv 60 i peak = ? = oc _ pk (min) sense i mv 40 r =
13 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary applications information applications information (cont.) designing the loop there are two aspects concerning the loop design. one is the power train design and the other is the external compensation design. a good loop design is a combination of the two. in the SC1403, the control-to-output/power train response is dominated by the load impedance, the effective current sense resistor, out- put capacitance, and the esr of the output caps. the low fre- quency gain is dominated by the output load impedance and the effective current sense resistor. inherent to virtual current sense tm , there is one additional low frequency pole sitting between 100hz and 1khz and a zero between 15khz and 25khz. to compensate for the SC1403 is easy since the output of error amplifier comp pin is available for external compensation. a traditional pole-zero- pole compensation is not necessary in the design using SC1403. to ensure high phase margin at crossover frequency while mini- mizing the component count, a simple high frequency pole is usu- ally sufficient. in the reference design below, single-pole compen- sation method is demonstrated. and the loop measurement re- sults are compared to that obtained from the simulation model. transient response is also done to validate the model. also, to help speeding up the design process, a list of recommended out- put caps vs. compensation caps value is given in table i. single-pole compensation method given parameters: vin = 19v, vout = 3.3v @ 2.2a, output impedance, ro = 3.3v/2.2a = 1.5 ? , panasonic sp cap, co = 180uf, resr = 15 ? m , output inductor, lo = 4.7uh switching frequency, fs = 300khz simulated control-to-output gain & phase response (up to 100khz) is plotted below . . measured control-to-output gain & phase response (up to 100khz) is plotted below. -200 -150 -100 -50 0 50 100 150 200 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) phase (deg) -50 -40 -30 -20 -10 0 10 20 30 40 50 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db) -200 -150 -100 -50 0 50 100 150 200 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) phase (deg) single-pole compensation of the error amplifier is achieved by connecting a 100pf capacitor from the comp pin of the SC1403 to ground. the simulated feedback gain & phase response (up to 100khz) is plotted below. -50 -40 -30 -20 -10 0 10 20 30 40 50 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db)
14 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary applications information (cont.) simulated overall gain & phase responses (up to 100khz) is plot- ted below. measured feedback gain & phase responses (up to 100khz) is plotted below. -15 -10 -5 0 5 10 15 20 25 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) phase (deg) -80 -60 -40 -20 0 20 40 60 80 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db) -20 0 20 40 60 80 100 120 140 160 180 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) phase (deg) -15 -10 -5 0 5 10 15 20 25 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 1.00e+02 1.00e+03 1.00e+04 1.00e+05 frequency (hz) phase (deg)
15 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary applications information (cont.) measured overall gain & phase response of the single-pole com- pensation using SC1403 is plotter below. table i. recommended compensation cap for different output capacitance. table i. is useful only if the following esr condition is satisfied. fo > 50khz where resr is the equivalent esr of the total output caps. -20 0 20 40 60 80 100 120 140 160 180 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) phase (deg) -80 -45 -10 25 60 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db) transient responses of the switcher using single-pole compensa- tion are shown below. the load steps from 0a to 3a and 3a to 6a. the applied di/dt is 2.5a/usec o esr o c r 2 1 f ? ? ? = p a c t u p t u on o i t a s n e p m o c d e d n e m m o c e r e u l a v p a c f 0 8 1 = f p 0 0 2 f 0 0 0 1 >f p 0 3 3
16 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary condtions: (psave enabled) vin = 10v, iload= 0a to 3a vout = 3.3v condtions: (psave disabled) vin = 10v, iload= 0a to 3a vout = 3.3v condtions: vin = 10v, iload= 3a to 6a vout = 3.3v condtions: (psave enabled) vin = 19v, iload= 0a to 3a vout = 3.3v typical characteristics
17 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary condtions: (psave disabled) vin = 19v, iload= 0a to 3a vout = 3.3v condtions: (psave enabled) vin = 10v, iload= 0a to 3a vout = 5.0v condtions: vin = 19v, iload= 3a to 6a vout = 3.3v condtions: (psave disabled) vin = 10v, iload= 0a to 3a vout = 5.0v typical characteristics (cont.)
18 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary condtions: vin = 10v, iload= 3a to 6a vout = 5.0v condtions: (psave enabled) vin = 19v, iload= 0a to 3a vout = 5.0v condtions: (psave disabled) vin = 19v, iload= 0a to 3a vout = 5.0v condtions: vin = 19v, iload= 3a to 6a vout = 5.0v typical characteristics (cont.)
19 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary applications information input capacitor selection input bulk capacitor is selected based on the input rms current requirement of the converter. the input rms ripple current can be calculated as follows: the worst case input rms current occurs at 50% duty cycle and therefore under this condition the irms current can be approxi- mated by therefore, for a maximum load current of 6a, the input capacitor should be able to handle 3a of ripple current. for the reference circuit design, there are two such regulators that operate out-of- phase. therefore, 3a ripple current is the most these two convert- ers will see under the normal steady state operating condition. for the combined two regulators, one smt os-con 47uf, 25v is used. the maximum allowable ripple current for the cap is rated 3.5a rms @ 100khz, 45 c . considering the derating at higher ambi- ent temperature and higher operating frequency, two additional mlc caps are also used (vishay mlc, 12uf, 25v, y5v, size 2225). choosing synchronous mosfet and schottky diode since this is a buck topology, the voltage and current ratings of the synchronous mosfet is the same as the main switching mosfet. it makes sense cost-volume-wise to use the same mosfet for the main switch as for the synchronous mosfet. therefore, sts12nf30l is used again in the design for synchronous mosfet. to improve overall efficiency, an external schottky diode is used in parallel to the synchronous mosfet. the freewheeling current is going into the schottky diode instead of the body diode of the synchronous mosfet, which usually has very high forward drop and slow transient behavior. it is really important when laying out the board, to place both the synchronous mosfet and schottky diode close to each other to reduce the current ramp-up and ramp- down time due to parasitic inductance between the channel of the mosfet and the schottky diode. the current rating of the schottky diode can be determined by the following equation, in out out in out rms v i ) v (v v i ? ? ? = 2 i i load rms = a 2 . 0 t n 100 i i s load avg _ f = ? = where 100nsec is the estimated time between the mosfet turn- ing off and the schottky diode taking over and ts = 3.33us. there- fore a schottky diode with a forward current of 0.5a is sufficient for this design. external feedback design in order to optimize the ripple voltage during power save mode, it is strongly recommended to use external voltage dividers (r10 and r9 for 5v power train; r8 and r11 for 3.3v power train) to achieve the required output voltages. in addition, a 56pf (c22 for 5v and c21 for 3.3v) cap is recommended connecting from the output to both feedback pins (pin # 3 and #12). the signal to noise ratio is therefore increased due to the added zeroes. input capacitor selection/out-of-phase switching the SC1403 uses out-of-phase switching between the two converters to reduce input ripple current, enabling the use of smaller, cheaper input capacitors when compared to in-phase switching. the two approaches are shown in the following figures. the first figure shows in-phase switching: i3in is the input current drawn by the 3.3v converter, i5in is the input current drawn by the 5v converter. the two converters start each switching cycle simultaneously, resulting in a significant amount of overlap. this overlap increases the peak current. the total input current to the converter is the third trace iin, which shows how the two currents add together. the fourth trace shows the current flowing in and out of the input capacitors. in-phase switching i3 i n i5 in iin average icap 0 0 the next figure shows out-of-phase switching. since the 3.3v and 5v converters are spaced apart, there is no resulting overlap. this results in a two benefits; the peak current is reduced and the frequency content is higher, both of which make filtering easier. the third trace shows the total input current, and the fourth trace shows the current in and out of the input capacitors. the rms value of this current is significantly lower than the in-phase case and allows for smaller capacitors due to reduced rms current ratings.
20 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary ic a p ii n average 0 0 i3 i n i5 i n as the input voltage is reduced, the duty cycle of both converters increases. for inputs less than 8.3 volts it is impossible to prevent overlap when producing 3.3v and 5v outputs, regardless of the phase relationship between the converters. this can be seen in the following figure. i3 i n i5 i n ii n 0 average ic a p 0 peri od phase l ead from an input filter standpoint it is desirable to make the minimize the overlap, but it is also desirable to keep the turn-on and turn-off transitions of the two converters separated in time, otherwise the two converters may affect each other due to switching noise. the SC1403 implements this by changing the phase relationship between the converter depending on the input voltage. e g a t l o v t u p n ig n i s i r r e t r e v n o c v 3 m o r f d a e l e s a h p e g d e g n i s i r r e t r e v n o c v 5 o t e g d e v 6 . 9 > n i vd o i r e p g n i h c t i w s f o % 1 4 v 7 . 6 > n i v > v 6 . 9d o i r e p g n i h c t i w s f o % 9 5 n i v > 7 . 6d o i r e p g n i h c t i w s f o % 4 6 vin > 9.6v: 3.3v turn-on leads 5v turn-on by 41% of the switching period. with vin > 9.6v it is always possible to achieve no overlap, which minimizes the input ripple current. at vin = 9.6v there is no overlap, but the 3.3v turn-on is nearing the 5v turn-off converter. 6.7 < vin < 9.6v: 3.3v turn-on leads 5v turn-on by 59% of the period. to prevent the 3v turn-on from coinciding with the 5v turn- off (which could affect either output), the 5v pulse is delayed in time slightly such that the 3v turn-on occurs before the 5v turn-off. this creates a small overlap between the 3v turn-on and the 5v turn-off, with a resulting slight increase in rms input ripple, but this is preferred since it greatly reduces noise problems caused by simultaneous transitions. note that at vin = 6.7, the 3v turn-off is nearing the 5v turn-on. vin < 6.7 volts: 3.3v turn-on leads 5v turn-on by 64% of the period. the 5v turn-on is delayed slightly more to add separation between the 3v turn-off and 5v turn-on. this leads to more overlap, but at this point overlap is unavoidable. input ripple current calculations: the following equations provide quick approximations for input ripple current: d3 = 3.3v duty cycle = 3.3/vin d5 = 5v duty cycle = 5/vin i3 = 3.3v load current i5 = 5v load current dovl = overlapping duty cycle of the 3v and 5v pulses, which varies according to input voltage: vin > 9.6v: dovl = 0 9.6v > vin > 6.7v: dovl = d5 - 0.41 6.7v > vin dovl = d5 - 0.36 irms_cap = isw_rms 2 iin 2 + iin = d3 . i3 + d5 . i5 (average current drawn from vin) isw_rms = rms current flowing into 3v and 5v smps (isw_rms) 2 = dovl . (i3 + i5) 2 + (d3 - dovl) . i3 2 + (d5 -dovl) . i5 2 the worst-case ripple current varies by application. for the case of i3 = i5 = 6a, the worst-case ripple occurs at vin = 7.5v, at which point the rms capacitor ripple current is 4.2 amps. to handle this the reference design uses 4 paralleled ceramic capacitors, (murata grm32nf51e106z, 10 uf 25v, size 1210). each capacitor is rated at 2.2 amps, allowing for derating at higher temperatures. out-of-phase switching
21 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary operation below 6v input the SC1403 will operate below 6v input voltage with careful design, but there are limitations. the first limitation is the maximum available duty cycle from the SC1403, which limits the obtainable output voltage. the design should minimize all circuit losses through the system in order to deliver maximum power to the output. a second limitation with operation below 6v is transient response. when load current increases rapidly, the output voltage drops slightly; the feedback loop normally increases duty cycle briefly to bring the output voltage back up. if duty cycle is already near the maximum limit, the duty cycle cannot increase enough to meet the demand, and the output voltage sags more than normal. this problem can not be solved by changing the feedback compensation, it is a function of the input voltage, duty cycle, and inductor and capacitor values. if an application requires 5v output from an input voltage below 6v, the following guidelines should be used: 1 - set the switching frequency to 200 khz (tie sync to gnd). this increases the maximum duty cycle compared to 300 khz operation. 2 - minimize the resistance in the power train. select mosfets, inductor, and current sense resistor to provide the lowest resistance as is practical. 3 - minimize the pcb resistance for all traces carrying high current. this includes traces to the input capacitors, mosfets and diodes, inductor, current sense resistor, and output capacitor. 4 - minimize the resistance between the SC1403 circuit and the power source (battery, battery charger, ac adaptor). 5 - use low esr capacitors on the input to prevent the input voltage dropping during on-time. 6 - if large load transients are expected, high capacitance and low esr capacitors should be used on both the input and output. overvoltage test measuring the overvoltage trip point can be problematic. any buck converter with synchronous mosfets can act as a boost converter, sending energy from output to input. in some cases the energy sent to the input is enough to drive the input voltage be- yond normal levels, causing input overvoltage. to prevent this, enable the SC1403 psave# feature, which effectively disables the low side mosfet drive so that little energy, if any, is transferred back to the input. semtech recommends the following circuit for measuring the ov- ervoltage trip point. d1 prevents the output voltage from damag- ing lab supply 1. r1 limits the amount of energy that can be cycled from the output to the input. r2 absorbs the energy that might flow from output to input, and d2 protects lab supply from pos- sible damage. the on5 signal is monitored to indicate when overvoltage occurs. initial conditions: both lab supplies set to zero volts no load connected to 3v or 5v psave# enabled (psave# tied to gnd) on5, on3 both enabled dvms monitoring on5 and the output under test. oscilloscope probe connected to phase node of the output under test (not strictly required). set lab supply 2 to provide 10v at the SC1403 input. the phase node of the output being tested should show some switching ac- tivity. the on5 pin should be above 4v. slowly increase lab supply 1 until the output under test rises slightly above it?s normal dc level. as the input lab supply 1 in- creases, switching activity at the phase node will cease. the on5 pin should remain above 4v. increase lab supply 1 in very small increments, monitoring both on5 and the output under test. the overvoltage trip point is the highest voltage seen at the output before on5 pulls low (approxi- mately 0.3v). do not record the voltage seen at the output after on5 has pulled low; when on5 pulls low, the current flowing in d1 changes, corrupting the voltage seen at the output. 1k d1 e.g. 1n4004 r2 75 to dvm d1 e.g. 1n4004 vin supply r1 470 2 SC1403 evaluation board lab output test under 1 supply lab to dvm 1/2w on5 vl 1/2w
22 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary typical characteristics 5v line regulation 4.99 4.995 5 5.005 5.01 5.015 5.02 5.025 5.03 10 12 14 16 18 20 22 24 vin (v) vout (v) 5v@0a 5v@3a 5v@6a 3.3v line regulation 3.31 3.315 3.32 3.325 3.33 3.335 3.34 10 12 14 16 18 20 22 24 vin (v) vout (v) 3.3v@0a 3.3v@3a 3.3v@6a
23 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary 5v load regulation @vin =19v 4.96 4.97 4.98 4.99 5 5.01 5.02 5.03 5.04 5.05 0123456 iout (a) vout (v) 5v @ 25degc 5v @125degc 5v@-45degc 5v load regulation @ vin =10v 4.95 4.96 4.97 4.98 4.99 5 5.01 5.02 5.03 0123456 iout (a) vout (v) 5.0v@25degc 5.0v@125degc 5.0v@-45degc typical characteristics (cont.)
24 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary 3.3v load regulation @ vin = 19v 3.29 3.3 3.31 3.32 3.33 3.34 3.35 0123456 iout (a) vout (v) 3.3v@125degc 3.3v@-45degc 3.3v@25degc 3.3v load regulation @ vin =10v 3.285 3.29 3.295 3.3 3.305 3.31 3.315 3.32 3.325 3.33 3.335 3.34 0123456 iout (a) vout (v) 3.3v@25degc 3.3v@125degc 3.3v@-45degc
25 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary 5v efficiency 85.00% 87.00% 89.00% 91.00% 93.00% 95.00% 97.00% 0.01 0.1 1 10 iout (a) efficiency (%) 5vout@19vin 5vout@10vin 3.3v efficiency 70.00% 75.00% 80.00% 85.00% 90.00% 95.00% 0.01 0.1 1 10 iout (a) efficiency (%) 3.3vout@19vin 3.3vout@10vin
26 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary evaluation board schematic dl3 vl j12 on3 1 c33 0.01uf d q3 irf7413 4 1 2 3 5 6 7 8 c1 10uf/25v 1 2 c26 no_pop 1 2 c22 no_pop 1 2 j9 ref 1 j19 b_jack_pair 1 2 pos neg r15 2m 1 2 c13 10 0 pf 1 2 c9 4.7uf/35v jp1 1 2 c omp3 j2 gnd 1 bst 5r d2 140t3 vl jp4 1 2 r ef lx 3 j5 gnd 1 vl l2 5.6uh c25 no_pop 1 2 r17 2m 1 2 c23 no_pop 1 2 dl5 j3 gnd 1 r13 no_pop 1 2 vin csh 5 c2 10uf/25v 1 2 c10 0.1uf r 1 10 1 2 on5_rc c 3 0.22uf r 6 0 1 2 jp5 1 2 d q4 irf7413 4 1 2 3 5 6 7 8 d4 14 0 t 3 csh 3 bst 5 d3 140t3 c20 no_pop c18 no_pop c14 10 0 pf 1 2 j18 b_jack_pair 1 2 pos neg c_5 jp2 1 2 c11 4.7uf/16v r16 2m 1 2 c12 0.1uf c16 0.22uf c omp5 r 4 8.06k 1 2 r 3 10 m 1 2 r31 0 1 2 r11 no_pop 1 2 c31 0.01uf +5v vi n c15 0.22uf d q1 irf7413 4 1 2 3 5 6 7 8 c6 10uf/25v 1 2 r 2 10 m 1 2 reset # r9 5m c omp5 c_3 lx 5 r 5 8.06k 1 2 jp6 1 2 shdn# on3 vl r 7 0 1 2 c21 0.1uf vin j10 sy nc 1 d q2 irf7413 4 1 2 3 5 6 7 8 ref bst 3 +5v c24 0.1uf sy nc bst 3r +3.3v v+ d5 14 0 t 3 vin_5v c29 0.1uf r12 no_pop 1 2 r14 2m 1 2 rtpa00024 1 SC1403 demonstration board b 13 t u es d ay , apr il 0 2 , 20 02 title size d o c um en t nu m b e r rev date: sheet of +3.3v c28 1uf/16v c17 18 0 uf / 4v seq j15 vl 1 jp3 1 2 t-on5 r19 2m 1 2 j1 b_jack_pair 1 2 pos neg c 4 0.22uf jp7 1 2 j16 sh dn# 1 fb5 j14 t- on5 1 r18 1k 1 2 l1 5.6uh c27 0.01uf reset# c19 15 0 uf / 6. 3v vin_3v c30 0.01uf r10 no_pop 1 2 dh 3 psv# j4 gnd 1 j24 v+s 1 dh 5 sw1 d ip_sw 5_pt h 1 2 3 4 5 10 9 8 7 6 fb3 j11 psv# 1 c5 10uf/25v 1 2 d 1 bat 54a u1 SC1403ts 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 csh 3 csl3 fb3 c omp3 c omp5 sy nc on5 gnd r ef psave r eset fb5 csl5 csh 5 seq dh 5 phase5 bst 5 dl5 pgnd vl v+ sh dn dl3 bst 3 phase3 dh 3 on3 r8 5m c omp3 j13 reset# 1 c32 0.01uf 1 2
27 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary m e t iy t i n a u qn o i t a n g i s e dr e b m u n t r a pn o i t p i r c s e dr e r u t c a f u n a me c i v e d 115 2 c5 0 1 c 1 b f 3 j c ev 6 1 , f u 1c i n o s a n a p6 0 2 1 217 1 cr 1 8 1 g 0 e u - f e ev 4 , f u 0 8 1c i n o s a n a p 3 4 3 7 _ e s a c _ d 319 1 cr 1 5 1 j 0 e u - f e ev 3 . 6 , f u 0 5 1c i n o s a n a p 3 4 3 7 _ e s a c _ d 42 9 2 c , 8 2 ck 5 0 1 a 1 b f 2 j c ev 0 1 , f u 1c i n o s a n a p5 0 8 511 da 4 5 t a bl a u d , a m 0 0 2 , v 0 3 e d o n a _ c x e t e z3 2 - t o s 64 5 d , 4 d , 3 d , 2 d3 t 0 4 1 s r b my k t t o h c s a 1 , v 0 4a l o r o t o mb m s 77 , 9 d , 8 d , 7 d , 6 d 2 1 d , 1 1 d , 0 1 d 6 1 2 3 r t p ad e l t n u o m e c a f r u st h g i r b g n i k6 0 2 1 87 , 4 p j , 3 p j , 2 p j , 1 p j 9 p j , 8 p j , 5 p j g r e b n i p 2 r o t c e n n o c g r e b 92 , 7 p j , 6 p jr o t c e n n o c g r e b n i p 3g r e b 0 13 7 j , 6 j , 1 jr i a p k c a j a n a n a b 1 13 1, 8 j , 5 j , 4 j , 3 j , 2 j , 3 1 j , 2 1 j , 1 1 j , 0 1 j 9 j 2 , 5 1 j , 4 1 j s t n i o p t s e t 2 12 2 l , 1 ls - m 6 r 5 - t 6 0 3 i l s sh u 6 . 5 r o t c u d n i t m st c a / o e g a y 3 14 4 q , 3 q , 2 q , 1 q3 1 4 7 f r il e n n a h c - n v 0 3 t e f s o m l a n o i t a n r e t n i r e i f i t c e r 8 o s 4 13 , 7 q , 6 q , 5 q1 t l 0 7 1 f b m mv 0 6 , a m 0 0 5 t e f l e n n a h c - n r o t c u d n o c i m e s - n o 3 2 t o s 5 111 ry n am h o 0 1y n a3 0 6 6 12 5 r , 4 ry n am h o 0y n a3 0 6 7 12 7 r , 6 r 3 4 b f 5 5 0 0 r 2 1 5 2 l s w m h o m 5 . 5e l a d y a h s i v2 1 5 2 8 14 7 1 r , 5 1 r , 2 1 r , 4 1 ry n am h o g e m 2y n a3 0 6 9 12 6 1 r , 8 2 ry n am h o k 1y n a3 0 6 0 24 6 2 r , 5 2 r , 3 2 r , 1 2 ry n am h o 7 3 . 2y n a3 0 6 1 22 9 1 r , 8 1 ry n am h o k 0 1y n a3 0 6 2 211 w s4 0 d bp i d n o i t i s o p - 4 h c t i w s k & c 3 211 us t 3 0 4 1 c sm w p e l i b o m s c v h t i w r e l l o r t n o c h c e t m e s8 2 p o s s t 4 213 u2 1 4 1 c se g r a h c d e t a l u g e r a m 0 2 1 h t i w p m u p t u p t u o h c e t m e s0 1 p o s m evaluation board bill of materials
28 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary m e t iy t i t n a u qr o t a n g i s e dr e b m u n t r a pn o i t p i r c s e dg n i r u t c a f u n a me c i v e d 5 2d 46 c , 5 c , 2 c , 1 c5 2 0 z 6 0 1 v 5 y 0 3 2 m r gv 5 2 , f u 0 1a t a r u m0 1 2 1 6 2d 11 1 cv 0 2 , f u 7 . 4e s a c _ b 7 2d 53 3 c , 6 2 c , 2 1 c , 0 1 ck 4 0 1 h 1 b y 2 - j c er 7 x , v 0 5 , f u 1 . 0c i n o s a n a p5 0 8 8 2d 28 c , 7 ck 1 0 1 h 1 b y 2 - j c er 7 x , v 0 5 , f p 0 0 1c i n o s a n a p3 0 6 9 2d 46 1 c , 5 1 c , 4 c , 3 cz 4 2 2 h 1 f v 2 - j c ev 5 y , v 0 5 , f u 2 2 . 0c i n o s a n a p5 0 8 0 3d 24 1 c , 3 1 ck 7 4 h 1 c v 1 j c ev 0 5 , f p 0 0 7 4c i n o s a n a p3 0 6 1 3d 32 3 c , 1 3 c , 0 3 cv 6 1 , f u 0 16 0 2 1 2 3d 17 2 ck 4 0 1 c 1 b v 1 j c ev 0 5 , f u 1 0 . 0c i n o s a n a p3 0 6 3 3d 15 2 c5 0 1 c 1 b f 3 j c ev 6 1 , f u 1c i n o s a n a p6 0 2 1 4 3d 24 2 r , 2 2 ry n am h o k 0 2y n a3 0 6 5 3d 23 r , 2 ry n am h o k 6 0 . 8y n a3 0 6 6 3d 19 2 ry n am h o 0 0 3y n a3 0 6 7 3d 17 2 ry n am h o 0 3 1y n a3 0 6 8 3d 13 1 ry n am h o k 0 0 1y n a3 0 6 evaluation board bill ofmaterials bottom assembly top assembly
29 ? 2002 semtech corp. www.semtech.com SC1403 power mana gement preliminary layout guidelines as with any high frequency switching regulator design, a good pcb layout is very essential in order to achieve optimum noise, effi- ciency, and stability performance of the converter. before starting to layout the pcb, a careful layout strategy is strongly recom- mended. see the pcb layout in the SC1403 evaluation kit manual for example. in most applications, we recommend to use fr4 with 4 or more layers and at least 2 oz copper (for output current up to 6a). use at least one inner layer for ground connection. and it is always a good practice to tie signal ground and power ground at one single point so that the signal ground is not easily contami- nated. also be sure that high current paths have low inductance and resistance by making trace widths as wide as possible and lengths as short as possible. properly decouple lines that pull large amounts of current in short periods of time. the following step by step layout strategy should be used in order to fully utilize the potential of SC1403. step #1. power train components placement. a. power train arrangement. place power train components first. the following figure shows the recommended power train arrangement. q1 is the main switching fet, q2 is the synchronous rectifier fet, d1 is the schottky diode and l1 is the output inductor. the phase node, where the source of upper switching fet and the drain of the synchronous rectifier meets, since it switches at very high rate of speed, is generally the largest source of common-mode noise in the converter cir- cuit. it should be kept to a minimum size consistent with its connectivity and current carrying requirements. also place the schottky diode as close to the phase node as possible to mini- mize the trace inductance, therefore reduce the efficiency loss due to the current ramp-up and down time. this becomes ex- tremely important when converter needs to handle high di/dt requirement. b. current sense. minimize the length of current sense signal trace. keep it less than 15mm. kevin connection should be used and try to keep the traces parallel to each other and have them close to each other as much as possible. even though SC1403 implements virtual cur- rent sense scheme, output signal is sampled by the SC1403 to determine the psave threshold. see the following figure for kelvin connection for current sense signal hook up. q2 d1 q1 l1 csh csl SC1403 rcs l1 c. gate drive. SC1403 has built-in gate drivers capable of sinking/sourcing 1a pk-pk. upper gate drive signals are noisier than the lower ones. therefore, place them away from sensitive analog circuitries. make sure the lower gate traces are as close as possible to the ic pins and both upper and lower gate traces as wide as possible. step #2: pwm controller placement (pins) and signal ground is- land. connect all analog grounds to a separate solid copper island plane, which connects to the SC1403?s gnd pin. this includes ref, fb3, fb5, comp3, comp5, sync, on3, on5, psv# and reset#. step #3: ground plane arrangement. there are several ways to tie the different grounds together. analog ground, power ground for the input side and power ground for the output side. since this is a buck topology converter, the output is relatively quieter than the input side. that is where we choose to tie the analog ground to the power ground through a 0 ? resistor. the power ground for the input side and the power ground for the output side is the same ground and they can be tied together using internal planes.
30 ? 2002 semtech corp. www.semtech.com SC1403 preliminary power management preliminary outline drawing - tssop-28 semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 contact information land pattern - tssop-28

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